1. Field of the Invention
The present invention relates to a digital wave shaping circuit, a frequency multiplying circuit, and an external synchronizing method and external synchronizing circuit, which produce digital signals, the phase of which is identical to the phase position of external trigger signals with the frequency thereof identical to the frequency of digital input signals.
2. Description of the Related Art
Generally, the interruption frequency of semiconductor active elements is definite, and the maximum usable frequency is subject to the limitation thereof.
For example, in FIG. 21, the wave forms of digital signals (1) and (2) have the same repeating frequency, f. However, because the ratio of the upside H level period TA to the downside L level period TB in the wave form of signal (2) is not equal to 1:1, whereas the ratio in the wave form of signal (1) is equal to 1:1 (50% duty cycle), the apparent (virtual) frequency of signal (2) is greater than the frequency of signal (1). The apparent frequency is important in the case of an IC of a semiconductor active element receiving an input signal having a wave form of 50% duty cycle, signal (1), and operating at the upper limit of its operational frequency. If the duty cycle of the input waveform is reduced to a smaller duty cycle (signal (2)), then the apparent frequency of the input wave form exceeds the operational frequency of the IC, and the IC is unable to respond to the apparent frequency of the input signal.
Therefore, it is preferable that digital signals have a wave form in which the ratio of period TA to period TB is equal to 1:1 (50% duty cycle). In other words, if the digital signals to be handled by semiconductor active elements have wave forms of 50% duty cycle, then the elements are able to handle digital signals of higher frequency.
In view of these points, a consideration is given of a digital wave shaping circuit, a frequency multiplying circuit, and an external synchronizing circuit.
(1) Digital Wave Shaping Circuit
Conventionally, in a synchronizing signal selection circuit which produces output signals, the frequency of which is identical to that of input signals and the phase of which is identical to the position of trigger signals, "n" sub reference signals Sa, Sb, SC, . . . of different phases are produced from a reference signal So. For example, a synchronizing signal selection circuit (disclosed by Japanese Patent Publication No. 95606 of 1986) shown in FIG. 22 receives a reference signal So of a frequency f ("m" is an integer number at least equal to 2) of the synchronizing output signal, and "n" sub reference signals Sa, Sb, Sc of different phases ("n" is an integer number at least equal to 2) are produced by gradually shifting the phase of the reference signal using delay elements DLI, DL2. The sub reference signals are frequency-divided by frequency dividers 823, 824, 825, wherein a trigger signal G is inputted into the frequency dividers, and the frequency-divided signals are logically synthesized in a logic circuit 822, thereby producing a synchronizing output signal.
Although, in the synchronizing signal selection circuit, it is necessary to handle reference signals of a frequency "m" times the repeating frequency f of the synchronizing output signal, the jitter is decreased in compliance with the number of the phase divisions, that is, the number "n" of the sub reference signals.
Thus, in the synchronizing signal selection circuit, it is important to produce "n" sub reference signals Sa, Sb, Sc of different phases from the reference signal So. Conventionally, a number of delay elements DLI, DL2, . . . are connected in series and are produced by carrying out an operation of gradually shifting the phases of the reference signal with the reference signal supplied into the delay elements.
However, with the above mentioned technique of gradually shifting the phase, a problem arises, in that, if a higher frequency (50 MHz to 100 MHz or the like) is handled, there are cases where a signal wave form is destroyed little by little as it passes through the respective delay elements and the meaning of the phase division is lost. In particular, even though it is assumed that the signal wave form entering the delay elements is a 50% duty cycle wave form, the wave form shifts from a 50% duty cycle by passing through the delay elements and its apparent frequency becomes higher, thereby causing an IC to exceed its maximum operational frequency.
Furthermore, with the above-mentioned technique of gradually shifting the phase, the jitter decreases with the number "n" of phase divisions, that is, sub reference signals. Therefore, in a case where a lower frequency (for example, 1 HZ or the like) is handled, the number of delay elements to be used is 2,000 to 3,000, wherein it is disadvantageous in the economical aspect and in view of heating of the elements.
Therefore, it is highly desirable, without depending on the above mentioned technique of gradually shifting the phases, to provide an actual wave form shaping circuit which is able to operate on waves and is constructed with as few number of semiconductor elements as possible.
(2) Frequency Multiplying Circuit
In the case where a frequency multiplier is able to a obtain 50% duty cycle, generally, the input digital signal (shifted from 50% duty cycle) is used as output after the signal is frequency-divided by two, and the phase is delayed 90 degrees. However, with the above, the frequency obtained will be the same as that of the initial input clock signal.
Therefore, it is considered that signals, the phase of which is shifted 45 degrees, 90 degrees and 135 degrees, are used.
However, in the case where such a technique of shifting phase is used, the construction of a frequency multiplying circuit is made complicated and the design has to be changed if the frequency to be handled is changed. Therefore, the target frequency is actually obtained by using a oscillator which has a frequency twice the frequency to be obtained and by dividing the frequency thereof.
Therefore, it is desirable to produce a frequency multiplying circuit, which is simple to construct, and which is able to output signals having a 50% duty cycle.
(3) External Synchronizing Circuit
Conventionally, in a clock signal generating circuit for writing color picture signals and a clock signal generating circuit for reading the signals, it is necessary to provide the circuits with an external synchronizing circuit which is able to generate clock signals in synchronization with horizontal synchronizing signals.
Conventionally, there is a synchronizing signal selection circuit, shown in FIG. 22, which produces signals, the frequency of which is identical to that of input signals and the phase of which is identical to the phase of trigger signals (Japanese patent publication No. 95606 of 1986). Since this circuit is explained above, the explanation about it is omitted here.
As stated above, with the conventional technique of gradually shifting the phase of the subreference signals, a problem arises, in that, if a higher frequency (50 MHz to 100 MHz or the like) is handled, there are cases where a signal wave form is destroyed little by little as it passes through the respective delay elements and the meaning of the phase division is lost. In particular, even though it is assumed that the signal wave form entering the delay elements is a 50% duty cycle wave form, the wave form shifts from the 50% duty cycle by passing through the delay elements and its apparent frequency becomes higher, causing an IC to exceed its maximum operational frequency.
Furthermore, with the above-mentioned technique of gradually shifting the phase, the jitter decreases with the number "n" of phase divisions, that is, sub reference signals. Therefore, in a case where a lower frequency (for example, 1 MHZ or the like) is handled, the number of delay elements to be used is 2,000 to 3,000, wherein it is disadvantageous in the economical aspect and in view of heating of the elements.
Therefore, it is highly desirable, without depending on the above-mentioned technique of gradually shifting the phases, to produce an external synchronizing circuit which is able to output clock signals synchronized with the trigger signals using as few number of semiconductor elements as possible.
Furthermore, in cases where external trigger signals fluctuated, conventionally it was difficult to automatically synchronize the output clocks to track the change.
Accordingly, it is desirable that an external synchronizing circuit, which is simple to construct, causes input clock signals to synchronize with external trigger signals and outputs signals in which the input digital signals are shaped to have a wave form of 50% duty cycle. To achieve this an external synchronizing method is proposed.
Furthermore, it is also desirable that an external synchronizing method and external synchronizing circuit are produced, which automatically cause the output clocks to synchronize with external trigger signals even though the external trigger signals fluctuate.
It is therefore the first object of the invention to provide a wave form shaping circuit which outputs signals having a duty cycle of 50% regardless of whether or not the input signals have a 50% duty cycle.
Furthermore, it is the second object of the invention to provide an actual frequency multiplying circuit having a simple construction, which is able to output signals wave forms having a duty cycle of 50%.
Still furthermore, it is the third object of the invention to provide an actual external synchronizing method and external synchronizing circuit having a simple construction, which are able to synchronize input clock signals with external trigger signals and to output input digital signals shaped to a wave form having a duty cycle of 50%. Furthermore, it is still another object of the invention to provide an external synchronizing method and external synchronizing circuit which are able to automatically synchronize output clocks to track external trigger signals even when they are fluctuating.